Nanjing Loyst Industrial Networks Co., Ltd.,

SIEMENS ERTEC 200P-2

nnnnOur company is distributing and supporting SIEMENS ERTEC 200P-2 as follows：

	nn The main features of ertec 200p-2 are：

	nnnIntegrated processor ARM926EJ-S	n nnOnchip Peripherals

	n n n√n125 / 250 MHz Core Frequency	n n n√nDMA Controller
	n n n√n16 KByte Data-Cache	n n n√n6 Timers
	n n n√n16 KByte Instruction-Cache	n n n√n2 Watchdogs
	n n n√n256 KByte TCM-RAM
	n n n√n8 KByte Boot ROM	n nnI/O Interfaces
	n n n√nLittle Endian
		n n n√n2 x 2 SPI Interfaces
	nnnSystem Bus Structure	n n n√n4 UARTs
		n n n√n1 I2C-Interface
	n n n√n32 Bit / 125 MHz AHB Bus	n n n√nOne 96-bit GPIO Port
	n n n√nMulti-Layer AHB Lite with 7	n n n√n1,8 / 3,3 V I/O Buffers
	n n nnnMasters and 12 Slaves
	n n n√nAHB Address Range Monitoring	n nnTest / Debug Functionality

	n nnLocal Bus Unit (XHIF)	n n n√nBoundary Scan
		n n n√nEJTAG for Debugging
	n n n√nAllows External Master to access
	n n nnninternal ERTEC 200P registers	n nnIntegrated Ethernet-Phy
	n n n√n16 / 32-Bit Data Bus
	n n n√n2 x 4 Paging Registers	n n n√n2 Ports
		n n n√nSupports 100Base-TX and -FX
	n nnMemory Controller (EMC)	n n n√nAuto Cross Over
		n n n√nAuto MDIX
	n n n√n8 / 16 / 32 Bit Data Bus	n n n√nJitter free Latency
	n n n√n4 chip selects
	n n n√nsupports SDRAM, SRAM, Burst	n nnPackage
	n n nnnMode Flash ROM
		n n n√n400 Pin FPBGA
		n n n√nSize 17 x 17 mm
		n n n√nBall Pitch 0,8mm

nFunctional Overview：

Figure 1: ERTEC 200P Step 1 and Step 2 Blockdiagram

	Key Functional Units

	1、Processor Core Subsystem (ARM926)

	n nnnARM926EJ-S Processor Core
	n nnn8 KByte Boot ROM
	n nnn256 KByte TCM-RAM
	n n √nEDC with 1-Bit Error Correction and 2-Bit Error Detection, with byte access
	n n √nconfigurable as Data (256-0 KByte) or Instruction (0-256 KByte)-RAM
	n n √nconfiguration-step: 64 KByte
	n nnnARM Interrupt Controller
	n n √nmax. 96 Interrupts
	n n √nmax. 8 fast Interrupts
	n n √n8 Software Interrupt inputs and 86 Hardware Interrupt inputs
	n nnnEmbedded Trace Macrocell (ETM9) for Debugging
	n nnnJTAG Block for Debugging
	n nnnMemory Management Unit (MMU) with Translation Lookaside Buffers (TLBs)
	n nnnseparate Data and Instruction-Bus

	2、Processor Bus Unit

	n nnnMemory Controller (EMC)
	n n—— SDRAM-Controller features:
	n n n √n16 / 32 bit databus width
	n n n √nPC133 SDRAM-compatible (125 MHz synchron is used)
	n n n √n1 Bank with max. 256 MByte SDRAM (32 Bit databus)
	n n n √nSDRAM support for following parts:
	n n n ·nCAS-Latency: 2 or 3 clocks
	n n n ·nBank-address bits (1/2/4 internal banks), realized via the lowest two bits of
	n n n n nthe address bus MA(1:0)
	n n n ·n8 / 9 / 10 / 11 bits column-address MA(13), MA(11:2)
	n n n ·nmax. 14 bits row-address MA(15:2)
	n n —— asynchronous controller features:
	n n n √n8 / 16 / 32 bit bus width (for each chip select programmable)
	n n n √n4 chip selects
	n n n √nthe timing for each chip select can be set individually
	n n n √nthe response to ready signal can be set individually for each chip select
	n n n √na maximum of 64 MByte address area for each chip select

	n nnnDMA Controller
	n n—— 1 Channel
	n n—— 31 Jobs
	n n n√n20 can be started from hardware
	n n n√n31 can be started from software

	n nnnTwo SPI Interfaces
	n n—— SPI1 via dedicated Pins
	n n—— SPI2 via GPIO Pins

	n nnnUART Interface via dedicated Pins

	n nnnTimer Unit (Module TIMER_TOP)
	n n—— … reloadable Down-Counters
	n n—— each Timer is equipped with a Multiplexer for Trigger Signals

	n nnnInterrupt Control Unit (Module ICU)
	n n—— level or edge triggered Operation
	n n—— 96 Interrupt Request Inputs
	n n—— Interrupt Priority is individually selectable for each Request Input

	n nnnWatchdog Unit (Module WDG1)
	n n—— Watchdog Interrupt Generation via Counter 0
	n n—— Watchdog Reset Generation via Counter 1
	n n—— Once started, the watchdog can only be stopped by a Power-On Reset.

	3、PROFINET – IP (PN-IP)

	n nnn2 Ethernet-Ports
	n nnn100MBit/s Ethernet-Port with integrated dual PHY
	n nnnDynamic Frame Packing
	n nnnFast Forwarding
	n nnnShort Preamble
	n nnnDynamic Fragmentation
	n nnnIRT-Forwarding
	n nnnPN-PLL
	n nnnSupport for Syncronisation-Protocolls (PTCP)

	4、Peripheral Interface (PER-IF)

	n nnnSupports Consistence for IO Data